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046B
CY7C1046B
1M x 4 Static RAM
Features
* High speed -- tAA = 12 ns * Low active power -- 935 mW (max.) * Low CMOS standby power (L version) -- 2.75 mW (max.) * 2.0V Data Retention (400 W at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features sion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1046B is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1046B is a high-performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory expan-
Logic Block Diagram
Pin Configuration
SOJ Top View
A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
INPUT BUFFER
ROW DECODER
I/O0
SENSE AMPS 1M x 4 ARRAY
I/O1 I/O2 I/O3
1046B-2 CE WE COLUMN DECODER POWER DOWN
A 11 A 12 A 13 A14 A15 A16 A17 A18 A19
OE
1046B-1
Selection Guide
7C1046B-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
7C1046B-15 15 150 8 0.5
7C1046B-20 20 130 8 0.5
12 170 Com'l L version 8 0.5
Cypress Semiconductor Corporation Document #: 38-05144 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 6, 2001
CY7C1046B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] ................................-0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature[2] 0C to +70C VCC 4.5V-5.5V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Com'l L version Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -1 7C1046B-12 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 170 20 2.2 -0.3 -1 -1 Max. 7C1046B-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 150 20 2.2 -0.3 -1 -1 Max. 7C1046B-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 130 20 Max. Unit V V V V A A mA mA
ISB2
8 0.5
8 0.5
8 0.5
mA
Shaded areas contain advance information.
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 6 Unit pF pF
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05144 Rev. **
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CY7C1046B
AC Test Loads and Waveforms
R1 481 R1 481 ALL INPUT PULSES Vcc 90% GND R2 255 10% 90%VCC 10%VCC
Fall Time:1 V/ns 1046B-4
5V OUTPUT 30 pF
5V OUTPUT R2 255 5 pF
INCLUDING JIG AND SCOPE (a) Equivalent to:
INCLUDING JIG AND SCOPE (b)
Rise Time:1 V/ns
1046B-3
THEVENIN EQUIVALENT 167 1.73V OUTPUT
Switching Characteristics[4] Over the Operating Range
7C1046B-12 Parameter READ CYCLE tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[7]
7C1046B-15 Min. 1 15 Max.
7C1046B-20 Min. 1 20 Max. Unit s ns 20 3 20 8 0 8 3 8 0 20 20 15 15 0 0 12 10 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 ns
Description
Min. 1 12
Max.
12 3 12 6 0 6 3 6 0 12 12 8 8 0 0 8 6 0 3 6 15 10 10 0 0 10 8 0 3 0 3 0 3
15 15 7 7 7 15
OE HIGH to High Z[6, 7]
[7] [6, 7]
CE HIGH to High Z
CE LOW to Power-Up CE HIGH to Power-Down
[8, 9]
WRITE CYCLE
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[7] [6, 7]
7
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05144 Rev. **
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CY7C1046B
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR tR
[3]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Com'l
Conditions[10] VCC = VDR = 2.0V, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V
Min. 2.0
Max 200
Unit V A ns s
0 200
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
1046B-5
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1046B-6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE
tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
1046B-7
HIGH IMPEDANCE
DATA OUT
ICC
Notes: 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05144 Rev. **
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CY7C1046B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID
1046B-8
tHA
tHD
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE
Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied.
tHD
DATAIN VALID
1046B-9
Document #: 38-05144 Rev. **
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CY7C1046B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
1046B-10
Ordering Information
Speed (ns) 12 15 20 12 15 20 Ordering Code CY7C1046B-12VC CY7C1046B-15VC CY7C1046B-20VC CY7C1046BL-12VC CY7C1046BL-15VC CY7C1046BL-20VC Package Name V33 V33 V33 V33 V33 V33 Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ Operating Range Commercial
Shaded areas contain advance information.
Document #: 38-05144 Rev. **
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CY7C1046B
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
Document #: 38-05144 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1046B
Document Title: CY7C1046B 1M x 4 Static RAM Document Number: 38-05144 REV. ** ECN NO. 109888 Issue Date 09/22/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00948 to 38-05144
Document #: 38-05144 Rev. **
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